The present invention generally relates to dynamic random access memories (DRAMs), and particularly relates to terminating write operations in synchronous DRAMs (SDRAMs).
Data transfers to and from an SDRAM are initiated by a memory controller. The memory controller provides a series of instructions to the SDRAM in the form of commands along with corresponding data. The SDRAM receives, interprets and executes the commands. The commands are issued by the memory controller, and processed by the SDRAM, in synchronization with a system clock. Likewise, data is written to and read from the SDRAM in synchronization with the system clock.
To achieve improved data transfer speeds, some types of SDRAMs, in particular, double-data rate SDRAMs (DDR SDRAMs), incorporate data strobe signals. In operation, data strobe signals are output by the device providing data and received by the device capturing, or sampling, the data. For example, during read operations, a DDR SDRAM outputs data signals and a corresponding data strobe signal for use by a memory controller. The memory controller samples the data signals using the data strobe signal as a timing reference. Likewise, during write operations, the DDR SDRAM samples data signals using the data strobe signal as a timing reference.
Transferring data to and from SDRAMs in “bursts” further improves SDRAM performance. The length of a data burst, commonly referred to as burst length, defines the maximum number of memory array column locations that are accessed during a particular read or write operation. Accessing multiple column locations during a single memory operation reduces the latency associated with activating blocks of SDRAM memory cells. Burst length is programmed during a hardware initialization process of the SDRAM. Once programmed, it generally is inefficient to modify the burst length during SDRAM operation. The burst length can be modified only when all SDRAM memory banks are idle and no bursts are in progress. Additionally, the memory controller must wait a specified time after modifying the burst length before initiating a subsequent operation. As such, conducting memory operations based on programmed burst lengths sometimes results in inefficiency, such as when there is a need to write data in amounts smaller than the programmed burst length.
Conventional SDRAMs may support early write termination in a number of known ways. That is, conventional SDRAMs may terminate or truncate an ongoing write operation before its completion, e.g., at less than a programmed burst length. However, conventional early write termination techniques come at the expense of performance, risk of uncertainty, or both. For example, early write termination may be accomplished by issuing a precharge command during an ongoing write operation. The precharge command deactivates the open row currently being written to. Deactivating the open row during a write operation prevents the write burst from completing. However, the deactivated row will be unavailable for a subsequent access until a precharge latency is satisfied. Thus, the deactivated row can not be written to or read from immediately after the precharge command is used for early write termination. In addition to the precharge latency, the row must be re-activated before another read or write command can be issued to the same row. This row activation process further increases the latency penalty associated with using the precharge command as a method of early write termination.
Issuing a subsequent read or write command during an ongoing write operation also results in early write termination. However, this requires the memory controller to issue an additional command and the SDRAM to interpret this command. Furthermore, data must be available for transmission to the SDRAM when the subsequent command is issued. Also, when terminating an ongoing write operation by issuing a subsequent read command, data masking may be required depending upon the write-to-read command interval. For example, if the write-to-read command interval is greater than one clock cycle, then data masking may be required.
Use of a burst stop command represents another option for early write termination. However, the burst stop command is well defined for read operations only. Use of the burst stop command during ongoing write operations may cause data uncertainty. That is, uncertainty may arise as to which data was or was not written to the SDRAM when the burst stop command was issued. Further, because use of the burst stop command for early write termination is not a standardized technique, its use for this purpose may cause SDRAM malfunction.